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Introduction: The Next Semiconductor Battle Is Moving Into the Machines
The semiconductor industry is approaching another major turning point. As chipmakers push toward smaller process nodes, the competition is no longer simply about who can manufacture the smallest transistor. It is increasingly about who can build those advanced chips reliably, economically, and at massive scale.
Samsung Electronics has now signaled a significant change in its roadmap for one of the most advanced lithography technologies in existence: High-NA EUV.
Instead of deploying High-NA EUV extensively for its upcoming 2nm and 1.4nm manufacturing processes, Samsung plans to delay full-scale commercial adoption until its A10, or 1nm-class, process. That means the technology is expected to become a major part of Samsung’s commercial production strategy around 2030.
The decision is not necessarily a sign that Samsung is abandoning High-NA EUV. Quite the opposite. It reflects a calculated decision to wait until the surrounding manufacturing ecosystem is mature enough to justify the enormous investment.
At the center of this decision is a difficult question: Is it better to deploy the world’s most advanced lithography equipment immediately, or wait until the technology can deliver its full economic and manufacturing benefits?
Samsung appears to have chosen the second path.
Samsung Changes Its High-NA EUV Roadmap
Samsung’s Semiconductor R&D Center has revealed that the company intends to postpone full-scale commercial deployment of High-NA EUV until its A10, or 1nm-class, process.
The information was presented by Park Chang-min, Master of Samsung’s Foundry Process Development Team, during the Next Generation Lithography + Patterning Conference, according to the supplied report.
Samsung had previously been expected to use High-NA EUV for earlier generations, including its 2nm and 1.4nm process technologies.
The
Instead of making High-NA EUV a central production technology for those nodes, Samsung plans to continue using conventional 0.33 numerical aperture EUV together with increasingly sophisticated multi-patterning techniques.
That approach could allow Samsung to continue advancing its process technology without immediately absorbing the enormous cost and manufacturing complexity associated with High-NA equipment.
What Is High-NA EUV?
High-NA EUV represents one of the biggest technological upgrades in modern semiconductor lithography.
Traditional EUV systems used in advanced manufacturing operate at a numerical aperture of approximately 0.33.
High-NA EUV increases that figure to approximately 0.55.
The increase may sound small, but its consequences are enormous.
Numerical aperture determines how effectively the lithography system can resolve extremely small structures on a silicon wafer. Increasing it allows manufacturers to print finer features with greater precision.
In practical terms, High-NA EUV can reduce the need for multiple patterning steps for certain extremely small structures.
That can potentially simplify manufacturing, reduce process complexity, and improve design flexibility.
But the technology introduces its own challenges.
Why Samsung Is Waiting
Samsung’s decision appears to be heavily influenced by the maturity of the High-NA ecosystem.
A lithography scanner is only one component of an advanced semiconductor manufacturing process.
Manufacturers also need suitable masks, pellicles, photoresists, materials, metrology systems, inspection equipment, process recipes, and supporting infrastructure.
If one part of that ecosystem is immature, the theoretical advantages of a new lithography platform can become much harder to realize in a high-volume production environment.
Samsung reportedly determined that several of these supporting technologies still require additional development.
That makes immediate mass deployment less attractive.
The Hidden Cost Behind High-NA EUV
High-NA EUV is not merely technologically complicated. It is extraordinarily expensive.
Each High-NA EUV machine is estimated to cost approximately $350 million to $400 million.
For a company building or expanding multiple semiconductor fabrication facilities, the financial implications quickly become enormous.
A production facility does not need just one lithography machine.
It needs multiple systems, supporting equipment, highly controlled cleanroom environments, specialized maintenance infrastructure, and extensive process-development capabilities.
The cost therefore extends far beyond the sticker price of the scanner itself.
Samsung has to consider whether High-NA EUV can generate enough manufacturing benefits at each process node to justify those investments.
Samsung’s Alternative: Mature EUV and Multi-Patterning
For its upcoming 2nm and 1.4nm-class manufacturing processes, Samsung intends to continue relying heavily on standard 0.33-NA EUV.
The company can combine that technology with multi-patterning techniques to create increasingly small and complex structures.
Multi-patterning is not a simple replacement for High-NA EUV.
It can require additional process steps, masks, and manufacturing complexity.
However, the technology is already much more mature.
That matters enormously in high-volume semiconductor production.
A mature process that produces predictable yields can sometimes be more valuable than a theoretically superior technology that has not yet reached manufacturing maturity.
The Semiconductor Industry Has a Timing Problem
The biggest challenge facing Samsung is not simply technological capability.
It is timing.
The semiconductor industry constantly pushes manufacturers toward smaller process nodes, but smaller does not automatically mean better business.
A new process must achieve acceptable yields, power efficiency, performance, wafer throughput, defect rates, and production costs.
If one of those factors becomes problematic, customers can hesitate to move major chip designs onto the new process.
This creates a dangerous cycle.
A foundry needs customers to justify investment, but customers need confidence that the foundry’s manufacturing technology is mature before committing expensive chip designs.
High-NA EUV adds another layer to that equation.
Intel Is Taking a Different Approach
Samsung is not alone in developing High-NA EUV.
Intel has already begun using High-NA EUV equipment for selected layers in chips associated with its 2nm-class manufacturing strategy.
The supplied report specifically identifies
Intel’s strategy demonstrates the competitive pressure surrounding this technology.
Rather than waiting for High-NA EUV to become relevant around the 1nm era, Intel is attempting to gain manufacturing experience with the platform earlier.
That could become an important advantage if High-NA EUV eventually becomes essential for leading-edge production.
TSMC Is Also Moving Carefully
TSMC appears to be taking a more conservative approach similar to Samsung’s in at least one important respect.
The company has acquired High-NA EUV equipment primarily for research and development and is expected to move toward commercial deployment around 2029 or 2030.
This is significant because it shows that
Instead, the industry appears to be divided between companies experimenting aggressively with early production applications and companies waiting for the broader ecosystem to mature.
The Real Battle Is Not Just About Lithography
The semiconductor race is often described as a competition between process nodes.
Samsung has 2nm.
TSMC has 2nm.
Intel has 18A and subsequent generations.
But the real competition is considerably more complicated.
The winner will not necessarily be the company that announces the smallest number first.
The winner will be the company capable of turning that technology into large volumes of high-quality chips at commercially attractive yields.
A process node that looks spectacular on a technical presentation but produces poor yields can become a financial disaster.
A slightly more conservative process that consistently produces working chips can become much more valuable.
Why 1nm Could Be the Right Moment
Samsung’s decision to target High-NA EUV for its A10, or 1nm-class process, is strategically interesting.
By approximately 2030, the technology ecosystem could be considerably more mature.
Mask technology should improve.
Pellicle technology should improve.
Materials should become more optimized.
Inspection systems should become more capable.
Manufacturing engineers will have more experience with High-NA platforms.
And semiconductor designers will have more practical knowledge about how to exploit the technology.
In other words, Samsung may be trying to avoid paying the early-adopter premium while still positioning itself for the generation where High-NA EUV becomes increasingly difficult to avoid.
The Risk of Waiting
However,
If Intel gains several years of practical High-NA manufacturing experience, it could develop valuable process knowledge before Samsung reaches large-scale deployment.
Manufacturing expertise is difficult to replicate quickly.
Yield optimization, defect management, patterning strategies, mask optimization, and process integration can take years to perfect.
If Intel turns its early High-NA investment into a significant production advantage, Samsung could eventually find itself playing catch-up.
The Risk of Moving Too Early
The opposite risk is equally important.
Deploying High-NA EUV before the ecosystem is ready could create enormous costs without delivering proportional manufacturing benefits.
A $400 million lithography system does not automatically translate into better economics.
If supporting materials remain immature or throughput is insufficient, the machine can become an expensive bottleneck rather than a competitive advantage.
Samsung therefore faces a classic technology-management dilemma.
Move early and risk paying for immature infrastructure.
Move late and risk losing manufacturing experience.
What This Means for Samsung Foundry
For Samsung Foundry, the decision may ultimately be about improving execution.
Samsung has invested heavily in advanced process technologies, including its 3nm and upcoming 2nm generations.
The
Delaying High-NA EUV could allow Samsung to concentrate its resources on improving current-generation process yields and customer adoption.
That may be more important in the short term than owning the newest lithography equipment.
The Importance of Yield
Yield may be the most underrated metric in semiconductor manufacturing.
Imagine two fabs producing advanced chips.
One uses extremely advanced equipment but has relatively poor yields.
The other uses a slightly older manufacturing approach but produces significantly more functional chips from each wafer.
The second facility can potentially have a much stronger business case.
This is why
It could instead represent a focus on manufacturing economics.
High-NA EUV Could Still Become Unavoidable
Even if Samsung delays widespread High-NA adoption, the technology’s long-term importance is difficult to ignore.
As transistor dimensions shrink, conventional EUV becomes increasingly dependent on complex patterning strategies.
At some point, additional patterning steps can create significant manufacturing penalties.
More steps can mean more processing time, more opportunities for defects, greater complexity, and potentially higher costs.
High-NA EUV offers a path toward reducing some of that complexity.
The question is not necessarily whether Samsung will use it.
The more important question is when the economics will make widespread deployment unavoidable.
The 2030 Semiconductor Landscape Could Look Very Different
By the time Samsung reaches A10 production, the semiconductor market may be dramatically different.
Artificial intelligence accelerators could dominate advanced-node demand.
Cloud companies could continue designing increasingly specialized processors.
Smartphones may use even more sophisticated AI architectures.
Automotive computing could require massive quantities of high-performance and highly efficient chips.
And semiconductor manufacturing itself could become even more strategically important to governments around the world.
In that environment, the ability to produce 1nm-class chips efficiently could become a major competitive asset.
What Undercode Say:
The Real Meaning Behind
Samsung’s High-NA decision should not be viewed simply as a delay.
It is a bet on timing.
The company is effectively saying that the technology is powerful, but the ecosystem is not yet mature enough to justify full-scale deployment at every advanced node.
That is a rational argument.
High-NA EUV is one of the most sophisticated manufacturing technologies ever developed.
Its value depends on an entire industrial ecosystem.
Samsung needs masks that can survive the process.
It needs pellicles capable of protecting those masks.
It needs materials engineered specifically for the new optical environment.
It needs inspection equipment capable of identifying extremely small defects.
It needs software capable of handling increasingly complex lithography optimization.
It needs process engineers with years of experience.
And it needs customers willing to design expensive chips around the resulting process.
That entire chain must mature together.
Samsung’s decision therefore reflects more than a hardware purchasing schedule.
It represents an assessment of industrial readiness.
The company appears willing to sacrifice some early High-NA experience in exchange for a potentially more stable deployment later.
That strategy could work extremely well if the ecosystem develops slowly.
It could become problematic if High-NA adoption accelerates much faster than expected.
Intel’s position is particularly interesting because early deployment can create a learning advantage.
Even if Intel does not immediately obtain dramatic cost benefits, its engineers are accumulating practical experience.
That experience could become extremely valuable as High-NA moves from experimental manufacturing into mainstream production.
TSMC’s slower commercial timeline suggests that Samsung is not completely out of step with the industry.
If TSMC also waits until around 2029 or 2030 for major commercial deployment, Samsung’s strategy could prove broadly aligned with the industry’s economic reality.
The most important question is therefore not who owns High-NA equipment today.
It is who can make it economically useful tomorrow.
Samsung’s traditional strength is its ability to combine semiconductor research, manufacturing infrastructure, memory technology, and enormous capital resources.
That gives the company room to make long-term bets.
But advanced foundry customers demand more than impressive technology announcements.
They want predictable yields.
They want reliable delivery.
They want competitive wafer economics.
They want confidence that a process will remain stable throughout the lifetime of their products.
That makes process maturity a strategic weapon.
The 2nm era will likely be a test of Samsung’s ability to turn advanced transistor technology into dependable mass production.
The 1nm era could then become the point where High-NA EUV determines how far the industry can continue scaling.
Samsung may therefore be positioning High-NA as the foundation for its next major manufacturing transition rather than spending heavily on it too early.
There is another important consideration: capital efficiency.
Every dollar invested in a High-NA scanner today is a dollar that cannot simultaneously be invested elsewhere.
Samsung must balance lithography spending against fab construction, advanced packaging, process research, chip design support, yield improvement, and customer acquisition.
That makes the decision much more complicated than simply buying the newest machine.
The semiconductor industry has entered an era where manufacturing economics can determine technological leadership.
A company can have the best transistor architecture in the world and still lose customers if it cannot manufacture chips efficiently.
Samsung’s High-NA strategy should therefore be watched alongside its 2nm yield progress, customer pipeline, packaging capabilities, and fab utilization.
Those indicators will reveal much more about the company’s competitive position than a single lithography announcement.
The next few years will also reveal whether Intel’s early High-NA strategy creates a meaningful advantage.
If Intel successfully integrates High-NA into selected production layers and achieves strong yields, competitors may be forced to accelerate their own adoption.
If Intel encounters serious throughput, cost, or ecosystem limitations, Samsung’s patience could look increasingly intelligent.
The same logic applies to TSMC.
If TSMC waits until the end of the decade and still achieves industry-leading manufacturing performance, it would demonstrate that early High-NA deployment is not necessarily essential.
The semiconductor industry is therefore conducting a massive real-world experiment.
Intel is moving earlier.
Samsung is waiting.
TSMC is researching and preparing.
The results will influence the next decade of chip manufacturing.
One thing is already clear: High-NA EUV will not be judged by how impressive its specifications look.
It will be judged by wafers.
It will be judged by yields.
It will be judged by throughput.
It will be judged by cost per functional chip.
And ultimately, it will be judged by whether customers choose to build their most valuable processors on the technology.
Deep Analysis: Watching
Monitor
Security and technology researchers can monitor public information related to Samsung’s semiconductor roadmap with simple Linux tools.
curl -L "https://www.samsung.com" -o samsung.html grep -iE "semiconductor|foundry|EUV|lithography" samsung.html
Search Local Research Notes
If you maintain a local intelligence archive, command-line search can quickly identify changes across saved reports.
grep -RniE "High-NA|0.55 NA|EUV|2nm|1.4nm|A10" ./research/
Compare Industry Timelines
A structured timeline can help distinguish announcements from actual manufacturing deployment.
grep -RniE "production|commercial|research|development|shipping" ./semiconductor-reports/
Track Equipment Economics
High-NA equipment costs should be evaluated alongside fab expansion rather than in isolation.
grep -RniE "\$350|\$400 million|High-NA|scanner|fab" ./industry-data/
Validate Reported Claims
For serious technology intelligence work, source comparison is essential.
sha256sum source-report.txt
A hash can help verify that an archived source has not changed after collection.
Watch the Ecosystem
The most important signals may come from outside Samsung itself.
Monitor developments involving masks, pellicles, photoresists, inspection systems, metrology, and advanced packaging.
Those technologies will determine how quickly High-NA can become commercially attractive.
Why the Commands Matter
The commands above are not about operating semiconductor equipment.
They represent a simple intelligence workflow: collect, search, compare, verify, and track changes over time.
That approach is particularly useful when technology roadmaps evolve over several years.
Accuracy of the Core Report
✅ Samsung’s High-NA EUV delay: The supplied report accurately describes Samsung’s stated intention to postpone full-scale commercial High-NA EUV adoption toward its 1nm-class A10 generation.
High-NA EUV Economics
✅ Equipment cost: The reported $350 million to $400 million estimated price range is consistent with widely reported expectations for High-NA EUV systems.
Industry Comparison
✅ Intel and TSMC: The comparison is broadly accurate: Intel has pursued earlier High-NA implementation on selected layers, while TSMC and Samsung have taken more measured approaches toward broad commercial deployment.
Prediction
(+1) High-NA EUV Becomes a Defining Technology of the 1nm Era
Samsung will likely continue developing High-NA EUV internally while relying on conventional EUV and multi-patterning for earlier generations.
By the end of the decade, supporting technologies should become substantially more mature.
High-NA EUV is likely to become increasingly important as conventional EUV patterning becomes more complicated.
Samsung’s A10 generation could become the point where the company’s High-NA strategy moves from preparation into large-scale manufacturing.
Intel’s early deployment could provide valuable manufacturing experience and pressure Samsung and TSMC to accelerate if major benefits emerge.
TSMC will likely remain cautious until the economics and ecosystem justify broader deployment.
(-1) The Biggest Risk for Samsung
If Intel converts early High-NA adoption into a significant yield or cost advantage, Samsung could face a difficult catch-up period.
If High-NA ecosystem development accelerates faster than Samsung expects, delaying deployment could reduce its competitive flexibility.
If customers demand High-NA-enabled manufacturing earlier than anticipated, Samsung may have to revise its roadmap.
The Bigger Picture
The High-NA EUV story is ultimately about more than one machine or one semiconductor manufacturer.
It is about how far humanity can continue shrinking electronic circuits while keeping advanced chip manufacturing economically viable.
Samsung is choosing patience.
Intel is choosing earlier experimentation.
TSMC is preparing carefully.
The outcome will help determine who controls the most advanced manufacturing capabilities of the 2030s.
For Samsung, postponing High-NA EUV may look conservative today. But if the ecosystem matures exactly as expected, the company could enter the 1nm era with a far more complete and economically viable technology stack.
The semiconductor race is entering another critical phase, and this time the winner may not be the company that moves first.
It may be the company that knows exactly when to move.
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