At any point of the digital transition,…
With all of the basic elements of IBM POWER10 Linux support in place, we’ve seen an uptick in IBM engineers’ POWER10 performance optimization patches in recent days. The upgrade of wake affine for sched/fair is the most noteworthy development this week. IBM traced part of the cause back to the Linux scheduling code after discovering that “POWER10 benchmark data is less than anticipated.”
Since the second-level cache in POWER10 is at the core level, certain scheduling/fairness changes have been made for POWER10, including cache affinity and preference for idle CPU cores. This patch collection, as well as the early April patch sequence, has made progress. The first set of patches ensures that the second-level cache is discovered correctly and that the SMT scheduling domain is set to the LLC domain.
The impact of these patches is immediately apparent; for example, the Java DayTrader benchmark test case reveals a 44 percent improvement in throughput, and the synthetic scheduling benchmark test has also been significantly enhanced. However, these patches are still being reviewed, and the original POWER9 hardware has not been checked to ensure that no regression to the old system occurs. These updates are too late for Linux 5.13 as the merger window approaches, but maybe the 5.14 kernel will complete the upstream merger later this year.
The entire Linux/open source community has also received some small updates for POWER10 in recent days and weeks. Glibc, for example, optimized Strlen for POWER10, and it also improved the string length feature significantly.
Customers are scheduled to receive IBM POWER10 system equipment by the end of the year, but further adjustments are expected in the coming months.